Title :
Analytic analysis of 77 K CMOS minimum channel length
Author :
Abramczyk, Edward R. ; Meindl, James D.
Author_Institution :
Stanford Univ., CA, USA
Abstract :
The device limits for 77 K CMOS are calculated using a new analytic solution to Poisson´s equation. Symmetric complementary devices with n/sup +/ polysilicon gate n-channels and p/sup +/ polysilicon gate p-channels are modeled. Laplace´s equation in the gate oxide and Poissons´s equation in the silicon are solved with Dirichlet boundary conditions. The surface potential is rigorously derived by requiring continuity of the potential and normal component of the displacement field. The device channel length limit L/sub min/=74 nm at 77 K is calculated. Carrier freezeout is minimized by the resulting surface channel operation.<>
Keywords :
CMOS integrated circuits; cryogenics; integrated circuit technology; surface potential; 74 nm; 77 K; CMOS; Dirichlet boundary conditions; Laplace´s equation; Poisson´s equation; Poissons´s equation; Si-SiO/sub 2/; analytic solution; carrier freezeout; device channel length limit; device limits; displacement field; minimum channel length; n/sup +/ polysilicon gate n-channels; p/sup +/ polysilicon gate p-channels; potential continuity; surface channel operation; surface potential; Boundary conditions; Capacitors; Dielectric constant; Laplace equations; MOS devices; Physics; Poisson equations; Semiconductor device modeling; Silicon compounds;
Conference_Titel :
Low Temperature Semiconductor Electronics, 1989., Proceedings of the Workshop on
Conference_Location :
Burlington, VT, USA
DOI :
10.1109/LTSE.1989.50186
