Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL

Author

Liu, Wu Ping ; Tan, Juan Boon ; Lu, Wei ; Pal, Shyam ; Siew, Yong Kong ; Cong, Hai ; Zhang, Bei Chao ; Wang, Xian Bin ; Zhang, Fan ; Hsia, Liang Choo

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

2005

Firstpage

70

Lastpage

71

Abstract

In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k < 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.

Keywords

chemical vapour deposition; dielectric thin films; photoresists; silicon compounds; wide band gap semiconductors; 90 nm; SiC; carbon-doped-oxide; dual damascene CDO film stack; dual damascene process architecture; etch-stop-layer; film stack deposition process; low-k BEOL; photoresist poisoning; Chaos; Copper; Dielectric substrates; Etching; Manufacturing processes; Nitrogen; Pulp manufacturing; Resists; Semiconductor films; Silicon carbide;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497085

Filename

1497085