• DocumentCode
    1731536
  • Title

    Vertical microvia connections achieved using a unique conductive composite material

  • Author

    Matijasevic, Goran ; Gandhi, Pradeep ; Gallagher, Catherine

  • Author_Institution
    Ormet Corp., Carlsbad, CA, USA
  • fYear
    1998
  • Firstpage
    306
  • Lastpage
    311
  • Abstract
    A novel base technology applicable to all major packaging and redistribution elements in an electronic module is presented. A unique polymer/metal composite conductor family based on transient liquid phase sintering (TLPS) can be used for chip package and PWB substrate applications, in interlayer connections, and for SMT assembly. High density multilayer circuits with landless blind and buried vias are fabricated by conductor paste filling of photoimaged dielectrics and thermal processing. Via layers are similarly prepared directly on the inherently planarized circuit layer. Circuit traces as fine as 50 /spl mu/m lines/spaces and vias as small as 75 /spl mu/m have been produced. Building up layers sequentially in this way allows additive fabrication on various materials, including metal substrates. These organic-metallic Ormet/sup (R)/ composites have also been used in interlayer connections between two-sided circuits to form vertical interconnects between circuit pads. This parallel build-up approach uses a standard lamination process to achieve vertical connections. Vias less than 100 /spl mu/m have been used to connect the pads. Fine line two-sided circuits can also be attached as a patch to low density boards to provide localized high density areas. Variations of the composite conductor can also replace solder for surface mount and COB assembly. These reliable, high thermal/electrical conductivity materials are compatible with standard metal finishes of conventional technologies and can be used piecemeal as desired, but the largest reliability and cost benefit is realized when all of the elements are used together.
  • Keywords
    assembling; chip-on-board packaging; composite materials; dielectric thin films; fine-pitch technology; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; printed circuits; sintering; surface mount technology; 100 micron; 50 micron; 75 micron; COB assembly; Ormet organic-metallic composites; PWB substrate; SMT assembly; additive fabrication; base technology; buried vias; chip package; circuit pads; circuit traces; composite conductor solder replacement; conductive composite material; conductor paste filling; cost benefit; electrical conductivity; electronic module; fine line two-sided circuits; inherently planarized circuit layer; interlayer connections; landless blind vias; line/space patterns; localized high density board areas; metal finishes; metal substrates; multilayer circuits; packaging; parallel build-up; photoimaged dielectrics; polymer/metal composite conductor; redistribution elements; reliability; sequential build-up layers; standard lamination process; surface mount assembly; thermal conductivity; thermal processing; transient liquid phase sintering; two-sided circuits; vertical interconnects; vertical microvia connections; via layers; via size; Assembly; Circuits; Conducting materials; Conductors; Dielectric substrates; Electronic packaging thermal management; Electronics packaging; Inorganic materials; Materials reliability; Thermal conductivity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IEMT/IMC Symposium, 2nd 1998
  • Conference_Location
    Tokyo, Japan
  • Print_ISBN
    0-7803-5090-1
  • Type

    conf

  • DOI
    10.1109/IEMTIM.1998.704665
  • Filename
    704665