Ways of achieving high-performance MRAMs

Recent MRAM developments and critical issues, such as universal memory requirements in the future, are discussed. Highly self-aligned techniques enable us to shrink cell size to the embedded-DRAM level. Toggle-mode MRAMs (L.Savtchenko et al. and M.Durlam et al., 2003) have a wide programming margin and a sufficiently small error rate for high-density memories, achieving cell stability. A large tunneling magnetoresistance (TMR) value is essential for high-speed read access, and MgO, as a tunnel barrier, promises to improve this drastically (W.H. Butler et al., 2001 and J. Mathon et al., 2001). The use of cladding bit lines (BLs) and word lines (WLs) has become a popular technique to reduce programming current. Moreover, adding an external magnetic field to a toggle-mode MRAM effectively reduces this. Finally, we briefly discuss spin transfer switching (STS) operation as a challenge to be faced in the future (J.C. Slonczewski, 1996).