Package-die co-optimization for improved performance and lower cost: A 32nm 10-core Xeon CPU case study

Increased current consumption and greater fragmentation of power domains in high performance microprocessors have led to higher supply noise profiles. This not only increases the net power dissipation of the chip but also degrades frequency performance. Optimization of the power supply networks for improved efficiency is therefore a key challenge. This paper describes a methodology and results for simultaneous optimization of die and package power supply networks leading to considerable power savings. The methodology is also shown to improve cost of the product through reduced warpage and improved yield.