Title :
Analog design trends and challenges in 28 and 20nm CMOS technology
Author :
Dautriche, Pierre
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
Market trends for Multimedia Application Processor go on pushing CMOS technology in nanometer range. This puts analog design community in a strange paradox with simultaneously big challenges and tremendous opportunities. Analog is more than ever a key ingredient of advanced SoC with high performances PLL, giga samples high speed serial links and embedded power management. Challenge appears while achieving very high level of analog performances in a non analog-optimized and moving environment, inducing design architecture change and development of new design methodology. Opportunities come when analyzing nanometer MOS device performances which are going beyond analog designer dreams. These tremendous performances open the door for new sets of applications such as embedded mmW, digitally boosted analog functions with new market opportunities. The talk will highlight this new analog era coming with nanometer technologies.
Keywords :
CMOS analogue integrated circuits; embedded systems; multimedia computing; nanotechnology; phase locked loops; system-on-chip; CMOS technology; SoC; analog design challenge; design architecture; digitally boosted analog function; embedded power management; giga sample; high performances PLL; high speed serial link; multimedia application processor; nanometer MOS device; size 20 nm; size 28 nm; CMOS integrated circuits; CMOS technology; Layout; Logic gates; MOS devices; Performance evaluation; System-on-a-chip;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2011.6044243
