A fault tolerant ATM switching architecture

This paper proposes a new fault-tolerant, self-routing, and high performance switching architecture for ATM networks based on multistage interconnection networks (MINs). It consists of two closely linked Banyan networks. Links are provided at every stage to allow cells to transfer to and from each plane. Reliability analysis shows that this architecture has a much fault-tolerance than some of the fault-tolerant ATM networks found in the literature. Simulation results also indicate that the proposed architecture offers better performance in terms of cell loss rates with or without the presence of faults in the network. The proposed architecture offers high throughput with acceptable cell delay time, low cost, simple routing, and priority of messages. Furthermore, the proposed switch architecture is modular in its design making it ideal for VLSI implementation