Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack

Author

Doris, B. ; Park, D.-G. ; Settlemyer, K. ; Jamison, P. ; Boyd, D. ; Li, Y. ; Hagan, J. ; Staendert, T. ; Mezzapelli, J. ; Dobuzinsky, D. ; Linder, B. ; Narayanan, V. ; Callegari, S. ; Gousev, E. ; Guarini, K. ; Jammy, R. ; Leong, M.

Author_Institution

Mircoelectronics Div., IBM Semicond. R&D Center, Hopewell Junction, NY, USA

fYear

2005

Firstpage

101

Lastpage

102

Abstract

We have demonstrated aggressively scaled high performance UTSOI replacement gate CMOS featuring a HfO₂/TaN gate stack which achieves T_inv of 17.5nm with greater than 100 times reduction in leakage compared to a SiON/poly-Si control sample. The atomic layer deposition process, used for the metal gate electrode material, enables the replacement gate structure to be robust at extremely small dimensions. An offset spacer together with the ultra-thin Si channel is used to demonstrate functional sub-25nm UTSOI replacement gate pFETs with high-k and metal gate for the first time. These results suggest that the replacement gate architecture is a viable option for future high performance CMOS technologies.

Keywords

CMOS integrated circuits; III-V semiconductors; atomic layer deposition; hafnium compounds; silicon-on-insulator; tantalum compounds; CMOS technology; HfO₂-TaN; atomic layer deposition; high-k gate stack; metal gate electrode material; replacement gate structure; silicon-on-insulator; ultra-thin SOI; Atomic layer deposition; CMOS technology; Dielectric materials; Doping; Gate leakage; High K dielectric materials; High-K gate dielectrics; Silicides; Silicon compounds; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497095

Filename

1497095