A genetic approach to analog module placement with simulated annealing

This paper presents a novel approach to analog module placement with the combination of genetic algorithm and simulated annealing. The approach is based on the bottom-left relative placement represented by binary tree. It is superior to the other three approaches which were implemented with pure simulated annealing or genetic algorithms. A fractional factorial experiment was conducted using an orthogonal array to study the algorithm parameters. A meta-GA was applied to determine the exact parameter values. The dedicated cost function covers the special requirements of analog integrated circuits. The experimental results show this promising algorithm makes the best performance with the least mean cost and standard deviation over all the other compared approaches.