Title :
Compact parallel multipliers using the sign-generate method in FPGA
Author :
Tagzout, S. ; Sahi, L.
Author_Institution :
Microelectron. Lab., CDTA, Algiers, Algeria
Abstract :
Multiply operations are fundamental to most DSP applications. In this paper, a novel method to compute parallel multiplication in Field Programmable Gate Array (FPGA), is presented. The basic idea consists in adapting the sign-generate algorithm to the constant coefficient and the variable by variable multipliers. Implementation examples are discussed to show how to increase parallel multipliers performances, especially in density
Keywords :
digital signal processing chips; field programmable gate arrays; multiplying circuits; DSP; FPGA; constant coefficient multiplier; field programmable gate array; parallel multiplier; sign-generate algorithm; variable by variable multiplier; Concurrent computing; Degradation; Delay; Digital signal processing; Field programmable gate arrays; Image processing; Radar applications; Radar imaging; Sonar applications; Table lookup;
Conference_Titel :
Microelectronics, 1997. Proceedings., 1997 21st International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-3664-X
DOI :
10.1109/ICMEL.1997.632969
