Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits

This paper compares several methods for determining an optimal non-zero clock skew schedule for synchronous digital VLSI circuits. The optimality of a given clock skew schedule which satisfies the circuit timing constraints is defined from the perspective of circuit timing reliability. This optimality is characterized by the deviation of the computed clock schedule from an ´ideal´ objective clock schedule. Both linear and quadratic programming (LP and QP) formulations of the clock skew scheduling problem are analyzed and a novel LP formulation is introduced. These formulations are compared using the ISCAS´89 suite of benchmark circuits. Mathematical optimization results are calculated using the large scale optimization package Lancelot.