A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO2)

Negative bias temperature instability (NBTI) causes the threshold voltage (V,) to shift with stressing time and is an increasingly important reliability issue with CMOS scaling. To continue scaling, FinFETs and FETs on hybrid orientation substrates are two new technologies that are under consideration. Recently, higher NBTI was reported for FinFETs in comparison to planar FETs and this higher NBTI was attributed to <110> orientation of the fin sidewall. In this paper, we present a systematic study of NBTI in <110> and <100> orientation pFETs with thermal SiON, plasma nitrided SiON, and thermal SiON/HfO₂ as gate dielectrics. The objective of the study is to compare NBTI in pFETs as a function of substrate orientation and gate dielectric films and to apply a recently proposed physics based model to the NBTI data for gaining insights into NBTI. Three main results are reported. (I) Measurements show that the NBTI is larger for <110> orientation in comparison to <100> for the thermal SiON and SiON/HfO₂ pFETs. In contrast, NBTI is independent of substrate orientation for the plasma nitrided SiON pFETs. (II) NBTI induced increase in positive charge density is larger for the plasma nitrided SiON pFETs in comparison to those for thermal SiON and SiON/HfO₂ pFETs. (III) The model provides good fits to V, shift versus stressing time data for various pFETs. Using the model fits, V_t shifts after 10 years stressing are estimated and compared for various pFETs. Model parameters attribute the enhanced NBTI in <110> orientation pFETS to higher bonded hydrogen densities at the oxide/Si interface for the case of thermal SiON and SiON/HfO₂ pFETs. Since model fitting parameters are independent of substrate orientation for pFETS with plasma nitrided SiON. a possible explanation is that the incorporation of bonded hydrogen at the silicon interface is determined predominantly by the plasma nitridation conditions.