ΣΔ modulators for low-power digitally intensive radio transmitters

Digitally enhanced wireless transmitters are gaining prominence due to their promise of greater integration, flexibility to adapt to varying SNR conditions, and performance and area benefit that comes with CMOS feature size reduction. One of the drawbacks of digitally assisted linear RF modulators has been the high power consumption in the digital core. This results from the use of high sample rates in the ΣΔ modulators and RFDACs at the end of the transmitter (Tx) chain. The alternative to ΣΔ modulation is to use high resolution, high-speed RFDAC in the Tx chain. In this work we discuss a new approach that increases the order of ΣΔ modulation and reduces the sample rate without compromising the overall system integration or stability. The proposed approach leads to significant reduction in the number of quantization levels as well as the sample rate of operation. Based on power simulation results, it is shown that this approach results in significant power savings of up to 1.7x when compared to state-of-the-art linear modulators that use ΣΔ modulation.