A 3.3 V 1 GHz high speed pipelined Booth multiplier

Author

Chow, Hwang-Cherng ; Wey, I-Chyn

Author_Institution

Inst. of Semicond. Technol., Chang Gung Univ., Kwei-Shan, Taiwan

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

In this paper, a new MBE (modified Booth encoding) encoder, and a new MBE decoder are proposed at the CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of a critical path by levelling the complex gate in the MBE decoder. As a result, the MBE decoder is never the speed bottleneck of a pipelined Booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1 GHz in a TSMC 0.35 μm process with a power consumption of only 100.52 mW.

Keywords

CMOS logic circuits; decoding; encoding; high-speed integrated circuits; multiplying circuits; pipeline arithmetic; 0.35 micron; 1 GHz; 100.52 mW; 3.3 V; MBE decoder; MBE encoder; TSMC CMOS process; glitch-free architecture; high speed multiplier architecture; high speed pipelined Booth multiplier; low voltage architecture; modified Booth encoding; partial-product generator; pipelined multiplier architecture; CMOS technology; Central Processing Unit; Decoding; Delay effects; Digital signal processors; Encoding; Energy consumption; Low voltage; Pipeline processing; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1009876

Filename

1009876