Title :
A robust self-resetting CMOS 32-bit parallel adder
Author :
Jung, Gunok ; Sundarajan, Venkat ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
This paper presents new circuit configurations for a more robust and efficient form of self-resetting CMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are difficult to design and are not robust over process, temperature and voltage variations. The new techniques replace delay chains with logic circuits that will create pulses at the correct times, independent of operational and environmental factors. These concepts are illustrated using a 32-bit parallel adder as a design example.
Keywords :
CMOS logic circuits; adders; carry logic; high-speed integrated circuits; logic design; parallel processing; 32 bit; CLA adder; CMOS parallel adder; carry look-ahead adder; high-performance SRCMOS circuits; high-speed implementation; logic circuits; robust self-resetting adder; Adders; CMOS logic circuits; Circuit simulation; Delay; Logic gates; Robustness; Signal generators; Temperature; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009880
