A robust self-resetting CMOS 32-bit parallel adder

This paper presents new circuit configurations for a more robust and efficient form of self-resetting CMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are difficult to design and are not robust over process, temperature and voltage variations. The new techniques replace delay chains with logic circuits that will create pulses at the correct times, independent of operational and environmental factors. These concepts are illustrated using a 32-bit parallel adder as a design example.