Low-power methodology issues in digital circuit design

Author

Kontiala, Mika ; Heinonen, Aarne ; Nurmi, Jari

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

Two circuit implementations were considered. First, the VHDL description of a matched filter was synthesized, and the design was completed with a place&route tool. Second, a full-custom circuit was designed with the same structure to compare the power dissipation of the circuits. A low-power flip-flop is introduced. Both circuits were extensively simulated with several 0.35 μm transistor models, different supply voltages, netlists including parasitic data, and temperature range of -55 to +125 degrees. The full-custom circuit consumed 25% of the power of the standard-cell circuit.

Keywords

cellular arrays; flip-flops; hardware description languages; logic design; low-power electronics; matched filters; 0.35 micron; 55 to 125 degC; VHDL; digital circuit; flip-flop; full-custom circuit; low-power design; matched filter; place and route tool; power dissipation; standard-cell circuit; transistor model; Adders; Circuit simulation; Circuit testing; Delay lines; Digital circuits; Energy consumption; Finite impulse response filter; Flip-flops; Matched filters; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1009885

Filename

1009885