Design and fabrication of a test chip for 3D integration process evaluation

Process compatibility evaluation and mechanical stress test are of great importance for 3D integration processes. This paper presents the design and fabrication of a test chip to evaluate a newly developed 3D integration scheme. For CMOS-compatibility evaluation, individual CMOS devices and integrated circuit modules together with through-silicon-vias (TSVs) are designed. To demonstrate the functionality of 3D integration, CMOS loop oscillators comprising 21 stage CMOS inverters located on two separate device wafers and interconnected with TSVs are designed. Mechanical stresses on the device substrate induced by 3D process are quantitatively evaluated by employing a 16×16 CMOS stress sensor array. The electrical performance of the TSVs is also characterized using special test structures. The test chip and its functions can be used to evaluate different 3D TSV processes.