Automatic topology selection and sizing of Class-D loop-filters for minimizing distortion

This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated for the design of an half-bridge Class-D loop filter topology for portable applications that achieves less than 0.005% THD at 340mW output power with a 3.3V supply in typical 0.18um CMOS technology.