Design of intra prediction module in H.264 and AVS dual modes video decoder chip

This paper introduces the structure of intra prediction module, which has been implemented with Verilog hardware language, in H.264 and AVS dual modes video decoder chip. Firstly, the video coding standards and their principle are introduced. Then a highly efficient hardware architecture is given based on the analysis of intra prediction algorithm in H.264 and AVS. This design reuses some modules according to the common of H.264 and AVS in architecture and algorithm, in particular the PE processing unit. The parallel pipeline and memory controller are also adopted to enhance the decoding efficiency. Finally, the design passes the FPGA verification, which its results of simulation and synthesis show that the timing and area requirements of chip design are both satisfied.