An efficient edge traces technique for 3D interconnection of stack chip

An efficient edge traces technique in the wafer level is proposed and implemented in this work, which can be applied to the fabrication of the stack chip. Experiments were conducted by stacking four test chips 100μm thick, and the configuration of the pad is based on the memory chip from the electronics company. The chips for stacking were fabricated successfully through dicing the wafer and curing the adhesives in the trench. When four chips were built up and metallized, the stack chip was 430μm high, which is comparable to that of the TSV. The electrical resistance of the interconnection was measured to be 5Ω, which can be improved further with modification. The interconnection quality of the stack chip was examined through 3D images obtained with the use of the CT and X-ray. The images showed that the interconnections were made successfully.