DocumentCode
1733294
Title
A Study of Outlier Analysis Techniques for Delay Testing
Author
Wu, Sean H. ; Drmanac, Dragoljub Gagi ; Wang, Li.-C.
Author_Institution
Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA
fYear
2008
Firstpage
1
Lastpage
10
Abstract
This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different approaches are studied, an Euclidean-distance based algorithm, random forest, and one-class support vector machine (SVM), from which more advanced methods are derived and analyzed. We conclude that one-class SVM using a polynomial kernel is most effective for detecting delay defects, while keeping overkills minimized. The best models were successfully validated and a feasible approach to delay testing using one-class SVM is proposed.
Keywords
integrated circuit testing; logic testing; polynomials; support vector machines; Euclidean-distance based algorithm; delay testing; one-class support vector machine; outlier analysis techniques; random forest; Accuracy; Algorithm design and analysis; Clocks; Delay effects; Frequency; Predictive models; Silicon; Support vector machines; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-2402-3
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2008.4700548
Filename
4700548
Link To Document