Prospects and limits in wafer-level-packaging of image sensors

The ongoing efforts of increasing the resolution of image sensors for consumer products and the simultaneous demand for small camera systems led to a miniaturization in pixel sizes down to 1.4 μm. This technological progress enables the fabrication of high pixel count imagers with comparably small dimensions (e.g. 9 MPix with 4.88 mm × 3.66 mm / 3 MPix with 2.86 mm × 2.15 mm). Further on, besides the impact of the pixel size on the lateral dimensions of the imager, manufacturing and packaging issues of the optical components and their integration with the imager influence the miniaturization. There are two effects which determine the lower limit of reasonable pixel miniaturization. Firstly, the increasing single-to-noise characteristics of the pixel leading to noisy images especially perturbing under low light conditions. Secondly, the diffraction limits which determines the smallest possible spot size when using a “perfect” lens without any spot blurring aberrations. As the latter depends from the f-number of the system, pixel miniaturization demands high speed lenses (low f-numbers) which additionally complicates the optical design and challenges their fabrication. The enabling key technology for wafer level packaging of camera systems based on top-side illuminated imagers are Through Silicon Vias (TSV) because they allow a redistribution on the backside of the wafer wherefore the active side remains unaffected and can be completely used for the optic assembly. Due to comparably relaxed pitches of the contact pads of mostly more than 100 μm in most imaging applications, tapered vias with a polymer passivation are the straight forward approach and an economic reasonable TSV technology. Spray coating of polymers allows the use of low cure temperature materials also with severe topographies while spin coating can be a low cost alternative for applications where low silicon thicknesses of 40 μm and below are allo- - wed. Wafer bonding is the bridging technology which finally has to integrate the optics and the sensor part. Wafer stacks of up to a few millimeters have to be handled which can exhibit topographies on their backside while maintaining an accurate alignment of better than 5 μm. The fabrication of camera packages using only wafer level technologies gets more complex and expensive the bigger the vertical dimension and/or the aspect ratio or shape of its comprising features becomes. The demands for a system integration on wafer level scales therefore with increasing pixel number and I/O - density. This paper outlines the prospects and limits of state of the art wafer-level-packaging technology for image sensor packaging with respect to the optical design. A process chain is presented for a micro camera device which was completely fabricated on wafer level having a die size of about 1 mm × 1 mm.