A heuristic DSP BIST insertion algorithm with minimum area overhead

In this paper, a new methodology for generating a self-testable data path with minimum area overhead in a minimum number of test sessions is presented. The main contribution is in the register allocation and binding algorithm, which is constructed from two phases. In the first phase, a number of self-adjacent registers configured as concurrent built-in logic block observation registers (CBILBO´s) are minimized. As the registers configured as BILBO´s that can work as either pattern generator or signature analyzer for the same module add a large cost to the constructed data path, phase 2 of the proposed algorithm tries to minimize occurrence of those registers whenever possible in a minimum number of test sessions. When the algorithm is applied to DSP applications, an improvement is achieved for both area overhead and interconnections.