Title :
DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor
Author :
Parulkar, Ishwar ; Anandakumar, Sriram ; Agarwal, Gaurav ; Liu, Gordon ; Rajan, Krishna ; Chiu, Frank ; Pendurkar, Rajesh
Author_Institution :
Sun Microsyst. Inc., Santa Clara, CA
Abstract :
The third generation CMT (chip multithreaded) microprocessor from Sun Microsystems has 16 cores and is optimized for high throughput without compromising high single thread performance. This paper describes the unique challenges faced in DFX of this complex CMT processor and the DFX solutions deployed. Some of the notable new DFX features include a highly configurable scan architecture, a memory test network that leverages functional access paths, BIST of special memories, and a test mode for running functional tests in the presence of non-deterministic serdes interfaces. Identification of chips with partially good cores and caches is supported in manufacturing for yield and in the field for availability.
Keywords :
microprocessor chips; chip multithreaded microprocessor; configurable scan architecture; memory test network; non-deterministic serdes interfaces; Availability; Built-in self-test; Manufacturing; Memory architecture; Microprocessors; Pins; Sun; System testing; Throughput; Yarn;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700552
