DocumentCode
1733671
Title
Study on TSV with new filling method and alloy for advanced 3D-SiP
Author
Tsukada, Akihiro ; Sato, Ryohei ; Sekine, Shigenobu ; Kimura, Ryuji ; Kishi, Keijiroh ; Sato, Yukihiro ; Iwata, Yoshiharu ; Murata, Hidenori
Author_Institution
Grad. Sch. of Eng., Osaka Univ., Suita, Japan
fYear
2011
Firstpage
1981
Lastpage
1986
Abstract
We focus on 3D-SiP using TSV´s as one possible breakthrough method that can overcome semiconductor scaling limits. To this point, despite numerous investigations, this method has not reached mass production due to many problems in processing, structure, mass production, reliability, etc... In particular, typical filling methods used in the current TSV such as Cu electro-plating, W-CVD and the like have poor manufacturability and are limited to holes with small aspect ratios making practical adoption a problematic. To overcome this obstacle, we have developed a new Bi-Sn liquid metal filling method that is completely different from previous methods. In this method, we first form a high aspect ratio (>;25) miniature via (about 1μm) using RIE dry etching on a Si wafer. Filling is performed by melting metal in a vacuum, and then applying pressure. For this purpose, we have developed a new Bi-Sn filler material that expands when it congeals, and can withstand temperatures >;250C. Our landmark method makes it possible to increase the speed of filling a TSV by over 10 times, i.e., several minutes for a 12 inch wafer, as well as make it possible to fill a TSV with super high aspect ratio. In this work we provide an overview of the method and report on the characteristics of the new filler material. As a result Compared with the Cu-TSV, there is almost no Keep Out Zone using this material. It was clearly shown that this contributes to increased gate density.
Keywords
alloys; melting; silicon; sputter etching; system-in-package; three-dimensional integrated circuits; 3D-SiP; Bi-Sn; RIE dry etching; TSV; alloy; liquid metal filling method; metal melting; semiconductor scaling limits; silicon wafer; Copper; Filling; Materials; Stress; Through-silicon vias; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location
Lake Buena Vista, FL
ISSN
0569-5503
Print_ISBN
978-1-61284-497-8
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2011.5898788
Filename
5898788
Link To Document