• DocumentCode
    1733823
  • Title

    Hardware implementation of Moore test on FPGA

  • Author

    Hisakado, Takashi ; Nishimura, Tsuneto ; Okumura, Kohshi

  • Author_Institution
    Dept. of Electr. Eng., Kyoto Univ., Japan
  • Volume
    1
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Abstract
    The Moore test is a powerful tool for finding all solutions of nonlinear equations. However, because the algorithm needs tremendously many interval computations, we can not apply the method to large dimensional systems. To overcome this difficulty, we propose the hardware implementation of Moore test on FPGA (Field Programmable Gate Array). We design the Moore test processor on FPGA and try to realize the system of finding all solutions by implementing the board on PCI bus of AT-compatible PC. Using the reconfigurability of FPGA, we can implement the algebraic equation and Krawczyk operator as well as the algorithm of Moore test on FPGA.
  • Keywords
    field programmable gate arrays; nonlinear equations; AT-compatible PC; FPGA processor; Krawczyk operator; Moore test algorithm; PCI bus; field programmable gate array; interval computation; nonlinear algebraic equation; reconfigurable hardware; Algorithm design and analysis; Arithmetic; Central Processing Unit; Circuit testing; Field programmable gate arrays; Hardware; Nonlinear equations; Programmable logic arrays; Registers; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
  • Print_ISBN
    0-7803-7448-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2002.1009925
  • Filename
    1009925