LSI packaging development for high-end CPU built into supercomputer

This paper reports on the development of CPU package for the next-generation supercomputer, besides a report of the assembly technology development of a large-scale BGA package that mounts large-scale chip. A large-scale LSI is mounted on CPU package developed this time. The size of a large-scale LSI is about 23.0×23.0mm. In addition, low permittivity (Low-k) material is adopted in interlayer dielectric in wiring layer. Because this Low-k material was fragile, being destroyed by stress that hangs in assembly became a problem. To clear this problem, the kind of the substrate was examined from the coefficient of thermal expansion. Moreover, the confirmation including an enough margin is done. The criterion was decided and the evaluation was executed. As a result, the Low-k layer was able to be prevented being destroyed. Next, it thought the control of void generated when under-fill was filled to be a critical. It is difficult because the chip size is large and there are a lot of numbers of solder bump. Best under-fill is selected an it was applied to this package. Finally, to accommodate to the demand value to severe thermal resistance, Cu-LID was selected as a high heat radiation structure. Additionally, the thermal interface material was adopted between the chip and Cu-LID. The amount of the warpage on the surface of Cu-LID was controlled to about 50 microns by this structure. Moreover, void of the metal joint was not generated, and either the wettability was satisfied. It passes the preprocessing and subsequent environmental test on JEDEC Level-4, and it thinks the package developed this time to be high-quality.