Title :
Design and implementation of high and low modulo (216 + 1) multiplier used in IDEA algorithm on FPGA
Author :
Elagooz, Salah ; Hamdy, Nabil ; Shehata, Khaled ; Helmy, Eng M.
Author_Institution :
Mil. Tech. Coll., Egypt
Abstract :
In this paper the design and the implementation of high and low modulo (216+1) multiplier used in the international data encryption algorithm (IDEA) is presented. The used mathematical formula for each multiplier is provided. The comparison between the high and the low modulo multiplier is discussed and the comparison is performed according to the following: the multiplier location in IDEA structure, the process whether encryption or decryption, the used inputs and keys, the number of gates and the maximum speed. Exploring the differences between them will result in the following: the correct encryption/decryption process, the complete definition of IDEA, increased number of gates in the design of high modulo multiplier to correct the zero input state problem, the ability to customize the IDEA and to increase the operating speed of the target IDEA chip. The two modulo multipliers are implemented on Xilinx FPGA Spartan II family and the target chip is XC2S100-5PQ208C.
Keywords :
cryptography; field programmable gate arrays; logic design; multiplying circuits; XC2S100-5PQ208C; Xilinx FPGA Spartan II family; decryption process; differential cryptanalysis; field programmable gate arrays; high modulo multiplier; international data encryption algorithm; linear cryptanalysis; low modulo multiplier; multiplier location; security; zero input state problem; Algorithm design and analysis; Cryptography; Data security; Delay; Educational institutions; Field programmable gate arrays; Throughput;
Conference_Titel :
Radio Science Conference, 2003. NRSC 2003. Proceedings of the Twentieth National
Print_ISBN :
977-5031-75-3
DOI :
10.1109/NRSC.2003.1217343
