Title :
Systematic modeling and simulation of DLL-based frequency multiplier
Author :
Gholami, M. ; Sharifkhani, M. ; Ebrahimi, A. ; Saeedi, S. ; Atarodi, M.
Author_Institution :
Sharif Univ. of Technol., Tehran, Iran
Abstract :
This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented.
Keywords :
circuit simulation; delay lock loops; frequency multipliers; DLL based frequency multiplier; Matlab; charge pump based delay locked loops; Clocks; Delay; Integrated circuit modeling; Jitter; Numerical models; Phase frequency detector; Phase locked loops; DLL; DLL modeling; MATLAB Simulink; delay locked loop; frequency synthesizer;
Conference_Titel :
Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on
Conference_Location :
Gammath
Print_ISBN :
978-1-4244-6816-4
DOI :
10.1109/SM2ACD.2010.5672340
