• DocumentCode
    1733980
  • Title

    Latency-constrained resynchronization for multiprocessor DSP implementation

  • Author

    Bhattacharyya, Shuvra S. ; Sriram, Sundararajan ; Lee, Edward A.

  • Author_Institution
    Semicond. Res. Lab., Hitachi America Ltd., San Jose, CA, USA
  • fYear
    1996
  • Firstpage
    365
  • Lastpage
    380
  • Abstract
    Resynchronization is a post-optimization for static multiprocessor schedules in which extraneous synchronization operations are introduced in such a way that the number of original synchronizations that consequently become redundant significantly exceeds the number of additional synchronizations. Redundant synchronizations are synchronization operations whose corresponding sequencing requirements are enforced completely by other synchronizations in the system. The amount of run-time overhead required for synchronization can be reduced significantly by eliminating redundant synchronizations. However, since additional serialization is imposed by the new synchronizations resynchronization can produce significant increase in latency. This paper addresses the problem of computing an optimal resynchronization (one that results in the lowest average rate at which synchronization operations have to be performed) among all resynchronizations that do not increase the latency beyond a prespecified upper bound Lmax . Our study is based on the context of self-timed execution of iterative data flow programs, which is an implementation model that has been applied extensively for digital signal processing systems
  • Keywords
    data flow computing; multiprocessing systems; processor scheduling; signal processing; synchronisation; digital signal processing systems; extraneous synchronization operations; iterative data flow programs; latency-constrained resynchronization; multiprocessor DSP implementation; optimal resynchronization; redundant synchronizations; run-time overhead; sequencing requirements; serialization; static multiprocessor schedules; upper bound; Context modeling; Contracts; Delay; Digital signal processing; Graphics; Laboratories; Multiprocessing systems; Runtime; USA Councils; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
  • Conference_Location
    Chicago, IL
  • ISSN
    2160-0511
  • Print_ISBN
    0-8186-7542-X
  • Type

    conf

  • DOI
    10.1109/ASAP.1996.542830
  • Filename
    542830