Title :
DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG
Author :
Ahrens, Heiko ; Schlagenhaft, Rolf ; Lang, Helmut ; Srinivasan, V. ; Bruzzano, Enrico
Author_Institution :
Freescale Semicond./STMicroelectronics, Munich
Abstract :
The implementation and validation of a common DFT architecture for a new product family of PowerPC based microprocessors for various automotive applications supporting highest quality levels and low-cost test is a big challenge. When this new architecture has to satisfy the requirements of two semiconductor companies using two different CAD flows based on different ATPG tools coming with incompatible on-chip scan compression solutions, the task becomes even more complex. This paper describes the result of this major effort and shows the problems encountered along the way.
Keywords :
automatic test pattern generation; automotive electronics; design for testability; microprocessor chips; ATPG tools; CAD flows; DFT; automotive microprocessors; dual vendor; on-chip scan compression; Automatic test pattern generation; Automotive engineering; Built-in self-test; CMOS process; CMOS technology; Control systems; Logic testing; Microprocessors; Portfolios; Voltage control;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700600
