Reduced-complexity Viterbi detector architectures for partial response signalling

The objective of this paper is to provide a general framework for optimizing the design of Viterbi detectors to achieve substantial reductions in hardware complexity as well as power consumption. Specific application of the framework to partial response systems is discussed. It is shown that the complexity of the add-compare-select unit for an N-state Viterbi detector is approximately N adders. Compared to conventional architectures, this represents a 50% savings for partial response signals of interest in magnetic storage