Solid-state modulator R+D for JLC

Summary form only given as follows. The klystron modulator for the Japan Linear Collider (JLC) is required to produce a 500 kV 530 A, 1.5 microseconds flat-top pulse to drive a pair of 75 MW PPM-klystrons. To improve modulator reliability and energy efficiency, we are developing a solid-state modulator with a 1:5 primary split pulse transformer. This modulator consists of two parallel modulator units each driving the transformer primary winding. Each modulator unit uses multiple solid-state IGBT modules stacked in series, and generates 50 kV 2650 A pulses. This allows fast overcurrent protection and much easier flat-top tuning of the output waveform. To study this type of modulator, a ten-stacked model modulator has been assembled and successfully tested. In this paper, we describe the modulator design, and the experimental results of the model modulator.