Sequential circuit test generation for IDDQ testing of bridging faults

Author

Higamit, Y. ; Maeda, Toshiyuki ; Kinoshita, Kozo

Author_Institution

Sch. of Eng., Osaka Univ., Japan

fYear

1997

Firstpage

12

Lastpage

16

Abstract

This paper presents a test generation method for sequential circuits assuming IDDQ testing. We consider external bridging faults and internal bridging faults as a target fault. Test generation for external bridging faults consists of three phases as (1) use of weighted random vectors, (2) set of target values on selected signal lines, (3) deterministic test generation for undetected faults. In order to detect internal bridging faults, we use a sequential test generator for stuck-at-faults. Finally experimental results for ISCAS´89 benchmark circuits are given.

Keywords

CMOS logic circuits; IDDQ testing; ISCAS´89 benchmark circuits; bridging faults; deterministic test generation; external bridging faults; internal bridging faults; sequential circuit test generation; signal lines; target fault; undetected faults; weighted random vectors; Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Performance evaluation; Sequential analysis; Sequential circuits; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on

Conference_Location

Washington, DC, USA

Print_ISBN

0-8186-8123-3

Type

conf

DOI

10.1109/IDDQ.1997.633006

Filename

633006