Enabling high-speed turbo-decoding through concurrent interleaving

Turbo-codes are among the most advanced channel coding schemes and are already part of the 3rd generation wireless communication standards. Future applications, however, will have a demand for higher throughput than the currently targeted 2 Mbit/s, leading to a need for highly parallelized architectures for turbo-decoding. Those where until now nearly infeasible because the component decoders are separated by interleavers, which form a bottleneck between them. This paper presents for the first time architectures that perform concurrent instead of sequential interleaving, thus widening the interleaver bottleneck and enabling parallelized high-speed turbo-decoders. As no limitations on the interleaver design are implied, standard compliant turbo-decoders for high throughput are now feasible. Optimizations for high degrees of parallelization are derived, applied, and validated using our simulated and synthesized register transfer level model. Thus, a whole design space is provided instead of just a single architecture.