SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects

Excessive power supply noise (PSN) during testing can erroneously cause good chips to fail the manufacturing test, thus leading to unnecessary yield loss. While there are some emerging methodologies such as PSN-aware test generation technique to tackle this problem, they are not readily applicable in modular system-on-a-chip (SoC) testing. This is because: (i). embedded core tests are usually prepared by core providers who are not knowledgeable about the SoC power distribution network; (ii) embedded cores are usually tested in parallel to reduce testing time, but the associated inter-core PSN effects are not considered in existing SoC test architecture design and optimization process. In this paper, we present a fast inter-core PSN estimation method and use it to guide the test scheduling process to solve the PSN-induced SoC test yield loss problem. In addition, upon observing that the PSN effects usually manifest themselves only during the capture phase for scan-tested cores, we introduce novel design for test (DfT) structures into SoC test controller to avoid PSN effects with negligible testing time penalty. Experimental results demonstrate the effectiveness of the proposed solution.