Observations of Supply-Voltage-Noise Dispersion in Sub-nsec

This paper describes observations of supply-voltage-noise dispersion by using a test structure fabricated with a 65-nm low-power process. The test structure can capture the phenomenon in two domains: One is a space domain. The 1 kbit probes distributed uniformly over the entire test-module region detect the spread of the noise, which is induced in the center of the module. The noise is generated by simultaneous activation of 8 kbit flip-flops (FF), which are placed in a dense area. Each delay probe consists of a short buffer-chain between a pair of FFs to detect the delay shift caused by voltage drop in the area. The other is a time domain. The probes being different in the length of the buffer-chains can capture the time dependency. The measurement results have revealed how the supply-voltage-noise spreads over the entire test-module region in a very short time (sub-nsec).