Dynamic stage matching for parallel pipeline A/D converters

Parallel time-interleaved analog-to-digital converters (ADCs) promise very high-speed performance and reasonable power consumption at the expense of silicon area. Unfortunately, timing and transfer function mismatches among the parallel converter channels introduce harmonic distortion, severely limiting the linearity. A new and simple method to reduce the mismatch-induced non-linearity is proposed in this paper for pipeline ADCs. Entire stages of the pipeline are randomly swapped to average out the corresponding offset and gain error mismatches. Detailed behavioral simulations show the effectiveness of the approach in a two-channels 10 bit, 200 MS/s, 9-stage pipeline ADC.