DocumentCode
1735452
Title
A 115mW 12-bit 50 MSPS pipelined ADC
Author
Mathur, Sumeet ; Das, Mrinal ; Tadeparthy, Preetam ; Ray, Sourja ; Mukherjee, Subhashish ; Dinakaran, B.L.
Author_Institution
Texas Instruments, India
Volume
1
fYear
2002
fDate
6/24/1905 12:00:00 AM
Abstract
High sampling rate ADCs are needed in several communications applications like cable modems, and wireless LANs. In this paper we present a low power pipelined ADC cell implemented in a 0.18 μm digital CMOS process. The ADC uses a 4-bit/stage architecture for reduced power and area. The ADC has been put on a test chip to verify performance and achieves -70dB THD performance for 10 MHz input at 50 MHz sampling rate.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; modems; pipeline processing; wireless LAN; 0.18 micron; 10 MHz; 115 mW; 12 bit; 4-bit/stage architecture; 50 MHz; THD performance; cable modems; digital CMOS process; low power cell; pipelined ADC; test chip; wireless LANs; CMOS process; Communication cables; Logic; MIM capacitors; Metal-insulator structures; Modems; Pipelines; Sampling methods; Switches; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1009990
Filename
1009990
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