Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion

Author

Vaz, B. ; Paulino, N. ; Goes, J. ; Costa, R. ; Tavares, R. ; Steiger-Garção, A.

Author_Institution

Campus da Faculdade de Ciencias e Tecnologia, UNINOVA - CRI, Monte Da Caparica, Portugal

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADCs. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that reducing the supply voltage does not necessarily increase the used energy per conversion.

Keywords

analogue-digital conversion; circuit optimisation; clocks; genetic algorithms; integrated circuit design; low-power electronics; pipeline processing; 1 pJ; 1.5 V; 10 bit; CMOS; clock-boosting techniques; genetic algorithms; low-voltage pipelined ADCs; multi-bit architectures; optimization methodology; power efficiency; supply voltage; switched-opamp techniques; Algorithm design and analysis; CMOS technology; Clocks; Design optimization; Energy resolution; Genetic algorithms; Image resolution; Pipelines; Power dissipation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1009992

Filename

1009992