DocumentCode
1735514
Title
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model
Author
Jayaraman, Dheepakkumaran ; Flanigan, Edward ; Tragoudas, Spyros
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL
fYear
2008
Firstpage
1
Lastpage
10
Abstract
This paper presents a novel approach for identifying non-robustly unsensitizable paths using the bounded delay model for gate delays. A unique feature is that the unsensitizable paths are identified by working on a data structure that stores selected circuit paths instead of the netlist. It is shown that unless the delay of untestable paths are ignored, many non-robust paths will remain undetected. Experimental results show the approach implicitly identifies a large number of non-robustly unsensitizable paths, which were not identified with other existing techniques.
Keywords
delays; integrated circuit testing; bounded delay model; gate delays; nonrobustly unsensitizable path detection; Circuit faults; Circuit noise; Circuit testing; Crosstalk; Data structures; Delay; Electrical fault detection; Fault diagnosis; Power supplies; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-2402-3
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2008.4700626
Filename
4700626
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