• DocumentCode
    1735560
  • Title

    IEEE 1500 Core Wrapper Optimization Techniques and Implementation

  • Author

    Mullane, Brendan ; Higgins, Michael ; MacNamee, Ciaran

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Univ. of Limerick, Limerick
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.
  • Keywords
    field programmable gate arrays; integrated circuit design; logic design; optimisation; IC-FPGA design flows; IEEE 1500 core wrapper optimization techniques; hybrid scan mode; logic overheads; vector formats; Automatic test pattern generation; Automatic testing; Circuit testing; Control systems; Design for testability; Field programmable gate arrays; Logic design; Logic testing; System testing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700629
  • Filename
    4700629
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1735560