Laser spike annealing for advanced CMOS devices

The introduction of new materials in recent years puts more stringent requirements on thermal budget management. For example, high Ge concentration in e-SiGe used for strain engineering makes wafers prone to thermal plastic deformation which limits the maximum annealing temperature. In this paper, we will explore ways to expand the process window using sub-millisecond laser spike annealing. Focus will be placed on thermal budget reduction and its impact on wafer warpage, Rs-Xj scaling and cross die temperature uniformity. Compatibility with high-k/metal gates and future non-planar device structures will also be discussed.