An Adjustable Clock Scan Structure for Reducing Testing Peak Power

Power consumption during testing is becoming a primary concern. In this paper, an adjustable clock scan structure is presented. It can significantly reduce the peak power consumption during testing. The adjustable clock controlling multiple scan chains is used to reduce SA (switching activity) and avoid simultaneous shifting operation. Compared with exiting techniques of low power scan testing, the adjustable clock scan structure has numerous advantages. It keeps peak power below a limit and maintains the same fault coverage. Moreover, it only takes up small DFT hardwires. Theoretical analysis and experiments on ISCAS89 benchmark circuits conformably show that the peak power consumption is reduced by about 60% during testing.