The Advantages of Limiting P1687 to a Restricted Subset

Modern semiconductor designs include an incredible amount of embedded logic in the name of DFx (which is largely comprised of design-for-test, design-for-debug, and design-for-yield content and will be called "instruments" in this paper). Most of this logic has the IEEE 1149.1 (JTAG) Test Access Port (TAP) and the JTAG TAP Controller as its primary access mechanism or, if not the primary, as one of its access mechanisms. The IEEE P1687 (IJTAG) Working Group is working to create a standard to deal with the "instrument" interfaces and optimal connection schemes. Part of that effort includes dealing with legacy logic and what some users have claimed are inefficient 1149.1 embedded logic connection schemes. This paper explores the advantages and efficiencies of restricting the instrument interfaces and connection scheme to exclude most legacy schemes.