FPGA implementation of a prototype PI Feedback control system for the LANSCE accelerator

The current LANSCE LLRF system is an analog PI Feedback control system which achieves amplitude and phase error of 1% and 1 degree respectively. The feedback system receives cavity amplitude and phase, crosstalk between the amplitude and phase paths is significant. We propose an In-phase (I) and Quadrature (Q) based feedback control system which easily decouples the crosstalk of the I and Q channels. A PI feedback controller is implemented with an Altera Stratix III FPGA. The control system is modeled with DSP Builder which automatically generates HDL. Altera SOPC Builder is used for the hardware integration of the DSP Builder model, memories, peripherals, and 32 bit NIOS II embedded processor. The NIOS II processor communicates with the host computer via Ethernet, uploads data, computes parameters, and downloads parameters. The network support of the design makes it possible to set and tune the control system parameters on-line and to conduct the calibration of the whole RF system easily. The proposed control system is successfully tested with a LANSCE sided-coupled linear accelerator at 720kw.