2.4-GHz 0.18-µm CMOS highly linear Power Amplifier

Author

Qian, Yongbing ; Li, Wenyuan ; Wang, Zhigong

Author_Institution

Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China

fYear

2010

Firstpage

210

Lastpage

212

Abstract

A Class-AB Power Amplifier (PA) integrated circuit for 2.4 GHz is presented. It is designed in SMIC 0.18 μm RF CMOS process. The PA adopts two-stage differential structure. The driver-stage uses cascode structure. In the output-stage common-source structure is employed. The proposed PA provides 24.8 dBm output power with a power-added efficiency (PAE) of 21.2% at 1 dB compression point. It has a small signal gain of 20.6 dB. The simulation results show that under a single 3.3 V supply voltage, the maximum output power reaches to 26.2 dBm. It can be used in IEEE 802.11b/g WLAN. The layout size is 1.4 × 0.75 mm².

Keywords

CMOS integrated circuits; power amplifiers; radiofrequency amplifiers; radiofrequency integrated circuits; IEEE 802.11 WLAN; SMIC RF CMOS process; cascode structure; class-AB power amplifier; efficiency 21.2 percent; frequency 2.4 GHz; gain 20.6 dB; linear power amplifier; output-stage common-source structure; size 0.18 mum; two-stage differential structure; voltage 3.3 V; CMOS integrated circuits; CMOS process; Layout; Power amplifiers; Power generation; Radio frequency; Simulation; 1dB compression point; CMOS PA; PAE; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Technologies for Communications (ATC), 2010 International Conference on

Conference_Location

Ho Chi Minh City

Print_ISBN

978-1-4244-8875-9

Type

conf

DOI

10.1109/ATC.2010.5672688

Filename

5672688