Breaking the 3D IC power delivery wall

Several power “walls” that must be overcome in future technologies are the 3D IC power delivery wall and the on-chip power regulation efficiency wall. In 3D ICs, power is consumed in the volume of the 3D chip, but can be delivered only to a 2D surface - as the number of layers in a 3D IC becomes larger, the greater the mismatch between 3D consumption and 2D delivery. The efficiency of on-chip regulators, which bounds the overall power efficiency of an IC, is not unique to 3D, but becomes essential due to the volumetric nature of the system. This paper studies voltage stacking of multi-layer heterogeneous 3D systems with distributed DC-to-DC on-chip regulators. The physical layering of 3D IC naturally maps to a voltage stacked solution that overcomes some of the difficulties with voltage stacking in 2D, such as isolating the stacked domains from the substrate. The paper presents a design methodology and optimization strategy for efficient on chip regulation using switch capacitor. Through simulation, we show how voltage stacked clustered layers can help overcome some of the limitations in 3D IC power delivery design.