Title :
A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies
Author_Institution :
Dept. of Electr. Eng., Auburn Univ., AL, USA
Abstract :
As device dimensions approach 0.1 /spl mu/m, analog effects will play an even larger role in digital circuits. IDDQ measurements can be significantly affected by the observed wafer to wafer (and even die to die) variations in electrical parameters. In this presentation we make a case for a Wafer Oriented Test Evaluation (WOTE) strategy where acceptable IDDQ thresholds are set based on the IDDQ measurements observed for the neighbouring die. Such an approach will minimize yield loss due to IDDQ testing while identifying defective die with abnormal IDDQ in comparison with their neighbours.
Keywords :
integrated circuit testing; 0.1 micron; IDDQ testing; IDDQ thresholds; analog effects; deep submicron technologies; defective die; digital circuits; wafer oriented test evaluation scheme; Circuit faults; Circuit optimization; Circuit testing; Digital circuits; Electrical fault detection; Fault detection; Leak detection; Probes; Rails; Wafer bonding;
Conference_Titel :
IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-8186-8123-3
DOI :
10.1109/IDDQ.1997.633011
