Jitters in high performance microprocessors

High performance microprocessors work with very little cycle time, usually within few hundreds of picoseconds nowadays. Since generating and routing a multiple GHz clock system on the motherboard is usually not possible, microprocessor clock is usually generated on chip with a PLL. While this has been a great advancement, this is not all nirvana yet. As great as an on-chip PLL is, the clock still have to be distributed to every state elements (i.e. latches, flops) on the chip, which amounts to millions spread over an area of up to 15 mm square. Realistically, there is the consideration of clock skew and also inevitably the jittering of those clock edges. Both of these cut into the useful cycle time, forcing a reduction of performance. Even the mighty PLL, due to its analog operation in nature, is also affected by process variations and the worsening of transistor performance with process scaling over the last 40 years. While clock skews and jitters on a board can be monitored and analyzed clock skews and jitters on a chip pose great difficulty. We cannot improve what we cannot observe, hence the observing and monitoring clock skews and jitters have been synonymous with high performance design for the last 10 years. This tutorial will present the sources of these skews and jitters and how they manifest and impact the performance of microprocessors. We will also show the effect of scaling on transistor performance and how it impacts the clock system. We will also present solutions that have been developed to overcome these hurdles.